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| author | Tony Lindgren <tony@atomide.com> | 2020-11-19 14:24:29 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2020-11-19 15:09:00 +0200 |
| commit | 57f57201360e443e7ec36124861a2e025d3d39ba (patch) | |
| tree | 19a6d25876fd53c9abe1ef917e4356313efa241d /drivers/clk/ti | |
| parent | fb0bf6aa8d5bd673d294b0b21b7c871d0308ae87 (diff) | |
| download | linux-57f57201360e443e7ec36124861a2e025d3d39ba.tar.gz linux-57f57201360e443e7ec36124861a2e025d3d39ba.tar.bz2 linux-57f57201360e443e7ec36124861a2e025d3d39ba.zip | |
clk: ti: dra7: Drop idlest polling from IVA clkctrl clocks
Similar to what we've done for IPU and DSP let's ignore the status bit
for the IVA clkctrl register.
The clkctrl status won't change unless the related rstctrl is deasserted,
and the rstctrl status won't change unless the clkctrl is enabled.
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'drivers/clk/ti')
| -rw-r--r-- | drivers/clk/ti/clk-7xx.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 4e27f88062e7..8b9118ccd4cd 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -252,6 +252,12 @@ static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initcons { 0 }, }; +static const struct omap_clkctrl_reg_data dra7_iva_clkctrl_regs[] __initconst = { + { DRA7_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h12x2_ck" }, + { DRA7_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, + { 0 }, +}; + static const char * const dra7_dss_dss_clk_parents[] __initconst = { "dpll_per_h12x2_ck", NULL, @@ -827,6 +833,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = { { 0x4a008c00, dra7_atl_clkctrl_regs }, { 0x4a008d20, dra7_l4cfg_clkctrl_regs }, { 0x4a008e20, dra7_l3instr_clkctrl_regs }, + { 0x4a008f20, dra7_iva_clkctrl_regs }, { 0x4a009020, dra7_cam_clkctrl_regs }, { 0x4a009120, dra7_dss_clkctrl_regs }, { 0x4a009220, dra7_gpu_clkctrl_regs }, |