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| author | Michael Chan <michael.chan@broadcom.com> | 2024-02-20 15:03:09 -0800 |
|---|---|---|
| committer | Paolo Abeni <pabeni@redhat.com> | 2024-02-22 15:31:22 +0100 |
| commit | ae8186b2d4064699e182682cff2ddc1c9486be38 (patch) | |
| tree | 486fb10d7fb7a998baa1df2b429505dd45b36211 /drivers/counter/intel-qep.c | |
| parent | 257bbf45af81bac9b0e38be530a554e2cff92700 (diff) | |
| download | linux-ae8186b2d4064699e182682cff2ddc1c9486be38.tar.gz linux-ae8186b2d4064699e182682cff2ddc1c9486be38.tar.bz2 linux-ae8186b2d4064699e182682cff2ddc1c9486be38.zip | |
bnxt_en: Explicitly specify P5 completion rings to reserve
The current code assumes that every RX ring group and every TX ring
requires a completion ring on P5_PLUS chips. Now that we have the
bnxt_hw_rings structure, add the cp_p5 field so that it can
be explicitly specified. This makes the logic more clear.
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Pavan Chebbi <pavan.chebbi@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'drivers/counter/intel-qep.c')
0 files changed, 0 insertions, 0 deletions