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authorHans de Goede <hdegoede@redhat.com>2023-05-29 11:37:41 +0100
committerMauro Carvalho Chehab <mchehab@kernel.org>2023-06-09 15:39:50 +0100
commit0af9078315c1a737675f041996c02582610b7cfd (patch)
tree87b8e44f00c59e538ec7923ead6e8b249f0c4336 /drivers/cpufreq
parente980fb04e779730b799a4ba712db901a7b08e8f9 (diff)
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media: atomisp: csi2-bridge: Set PMC clk-rate for sensors to 19.2 MHz
The ACPI code takes care of enabling/disabling the PMC clk(s) for the sensors as necessary based on the runtime-pm state of the sensor. But the GMIN code this replaces also set the clk-rate of the PMC clk to 19.2 MHz. At least on BYT devices the PMC clks may come up running at 25 MHz instead of the expected 19.2 MHz. Ensure the sensor clk also runs at the expected 19.2 MHz for sensors using v4l2-async probing by explicitly setting it to 19.2 MHz when enumerating sensors in atomisp_csi2_bridge.c. Link: https://lore.kernel.org/r/20230529103741.11904-22-hdegoede@redhat.com Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Diffstat (limited to 'drivers/cpufreq')
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