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| author | Weili Qian <qianweili@huawei.com> | 2022-09-24 18:34:45 +0800 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2022-10-21 19:05:23 +0800 |
| commit | 94adb03fd58bbe355e3d7a9d0f701889313e4a51 (patch) | |
| tree | 6db13dd40defa0fb126865e4ff3b5436735c7816 /drivers/crypto | |
| parent | f57e292897cac13b6ddee078aea21173b234ecb7 (diff) | |
| download | linux-94adb03fd58bbe355e3d7a9d0f701889313e4a51.tar.gz linux-94adb03fd58bbe355e3d7a9d0f701889313e4a51.tar.bz2 linux-94adb03fd58bbe355e3d7a9d0f701889313e4a51.zip | |
crypto: hisilicon/sec - enabling clock gating of the address prefetch module
Change the value of clock gating register to 0x7fff to enable
clock gating of the address prefetch module. When the device is
idle, the clock is turned off to save power.
Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto')
| -rw-r--r-- | drivers/crypto/hisilicon/sec2/sec_main.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c index 3705412bac5f..6eb8a16ba0a7 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -55,7 +55,7 @@ #define SEC_CONTROL_REG 0x301200 #define SEC_DYNAMIC_GATE_REG 0x30121c #define SEC_CORE_AUTO_GATE 0x30212c -#define SEC_DYNAMIC_GATE_EN 0x7bff +#define SEC_DYNAMIC_GATE_EN 0x7fff #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0) #define SEC_CLK_GATE_ENABLE BIT(3) #define SEC_CLK_GATE_DISABLE (~BIT(3)) |