summaryrefslogtreecommitdiffstats
path: root/drivers/cxl/cxl.h
diff options
context:
space:
mode:
authorDan Williams <dan.j.williams@intel.com>2023-04-03 14:33:48 -0700
committerDan Williams <dan.j.williams@intel.com>2023-04-04 15:34:34 -0700
commitb70c2cf95ee1ca2806cb7191504920f8f5b4454e (patch)
treedd73af470778eaaafc965ce8d1e685664a20c90a /drivers/cxl/cxl.h
parent82f0832af26a30ae5f21b335c5f68b538e710c29 (diff)
downloadlinux-b70c2cf95ee1ca2806cb7191504920f8f5b4454e.tar.gz
linux-b70c2cf95ee1ca2806cb7191504920f8f5b4454e.tar.bz2
linux-b70c2cf95ee1ca2806cb7191504920f8f5b4454e.zip
cxl/hdm: Skip emulation when driver manages mem_enable
If the driver is allowed to enable memory operation itself then it can also turn on HDM decoder support at will. With this the second call to cxl_setup_hdm_decoder_from_dvsec(), when an HDM decoder is not committed, is not needed. Fixes: b777e9bec960 ("cxl/hdm: Emulate HDM decoder from DVSEC range registers") Link: http://lore.kernel.org/r/20230220113657.000042e1@huawei.com Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/167703068474.185722.664126485486344246.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxl.h')
-rw-r--r--drivers/cxl/cxl.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index f2b0962a552d..aab87d74474d 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -695,13 +695,15 @@ int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint)
/**
* struct cxl_endpoint_dvsec_info - Cached DVSEC info
- * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
+ * @mem_enabled: cached value of mem_enabled in the DVSEC at init time
* @ranges: Number of active HDM ranges this device uses.
+ * @port: endpoint port associated with this info instance
* @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
*/
struct cxl_endpoint_dvsec_info {
bool mem_enabled;
int ranges;
+ struct cxl_port *port;
struct range dvsec_range[2];
};