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| author | Dave Jiang <dave.jiang@intel.com> | 2023-05-18 14:54:34 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-05-18 16:42:41 -0700 |
| commit | ce17ad0d54985e2595a3e615fda31df61808a08c (patch) | |
| tree | ceec13baa960bc056518ed8cfd5dcb879e6671c7 /drivers/cxl/pci.c | |
| parent | eb0764b822b9b26880b28ccb9100b2983e01bc17 (diff) | |
| download | linux-ce17ad0d54985e2595a3e615fda31df61808a08c.tar.gz linux-ce17ad0d54985e2595a3e615fda31df61808a08c.tar.bz2 linux-ce17ad0d54985e2595a3e615fda31df61808a08c.zip | |
cxl: Wait Memory_Info_Valid before access memory related info
The Memory_Info_Valid bit (CXL 3.0 8.1.3.8.2) indicates that the CXL
Range Size High and Size Low registers are valid. The bit must be set
within 1 second of reset deassertion to the device. Check valid bit
before we check the Memory_Active bit when waiting for
cxl_await_media_ready() to ensure that the memory info is valid for
consumption. Also ensures both DVSEC ranges 1 and 2 are ready if DVSEC
Capability indicates they are both supported.
Fixes: 523e594d9cc0 ("cxl/pci: Implement wait for media active")
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/168444687469.3134781.11033518965387297327.stgit@djiang5-mobl3
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/pci.c')
0 files changed, 0 insertions, 0 deletions