diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2022-03-14 18:22:28 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-04-12 19:11:58 -0700 |
| commit | e39f9be08d9dfe685c8a325ac1755c04f383effc (patch) | |
| tree | 19b77b6432f6bb9d2d83af20d1fa4e66bc997645 /drivers/cxl/pci.c | |
| parent | e08063fb87944b1db963e94b833608318179708d (diff) | |
| download | linux-e39f9be08d9dfe685c8a325ac1755c04f383effc.tar.gz linux-e39f9be08d9dfe685c8a325ac1755c04f383effc.tar.bz2 linux-e39f9be08d9dfe685c8a325ac1755c04f383effc.zip | |
cxl/pci: Add debug for DVSEC range init failures
In preparation for not treating DVSEC range initialization failures as
fatal to cxl_pci_probe() add individual dev_dbg() statements for each of
the major failure reasons in cxl_dvsec_ranges().
The rationale for cxl_dvsec_ranges() failure not being fatal is that
there is still value for cxl_pci to enable mailbox operations even if
CXL.mem operation is disabled.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Link: https://lore.kernel.org/r/164730734812.3806189.2726330688692684104.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/pci.c')
| -rw-r--r-- | drivers/cxl/pci.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 39694cc63381..1cb2557d68b7 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -467,12 +467,15 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds) { struct cxl_endpoint_dvsec_info *info = &cxlds->info; struct pci_dev *pdev = to_pci_dev(cxlds->dev); + struct device *dev = &pdev->dev; int d = cxlds->cxl_dvsec; int hdm_count, rc, i; u16 cap, ctrl; - if (!d) + if (!d) { + dev_dbg(dev, "No DVSEC Capability\n"); return -ENXIO; + } rc = pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap); if (rc) @@ -482,8 +485,10 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds) if (rc) return rc; - if (!(cap & CXL_DVSEC_MEM_CAPABLE)) + if (!(cap & CXL_DVSEC_MEM_CAPABLE)) { + dev_dbg(dev, "Not MEM Capable\n"); return -ENXIO; + } /* * It is not allowed by spec for MEM.capable to be set and have 0 legacy @@ -496,8 +501,10 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds) return -EINVAL; rc = wait_for_valid(cxlds); - if (rc) + if (rc) { + dev_dbg(dev, "Failure awaiting MEM_INFO_VALID (%d)\n", rc); return rc; + } info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); |