diff options
author | Yong Wang <yong.y.wang@intel.com> | 2010-10-04 10:37:27 +0000 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2010-10-07 15:03:43 -0700 |
commit | 03b96dca010145f3896abcd443b7fddb9813a0e6 (patch) | |
tree | 53fe9bffa5a23b1b4e49f953a9d8eb23f4b79935 /drivers/dma | |
parent | b306df5e925bb584b2157f11f97c5eb20a13de4d (diff) | |
download | linux-03b96dca010145f3896abcd443b7fddb9813a0e6.tar.gz linux-03b96dca010145f3896abcd443b7fddb9813a0e6.tar.bz2 linux-03b96dca010145f3896abcd443b7fddb9813a0e6.zip |
intel_mid_dma: Allow DMAC2 to share interrupt
Allow DMAC2 to share interrupt since exclusive interrupt line
for mrst DMAC2 is not provided on other platforms.
Signed-off-by: Yong Wang <yong.y.wang@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r-- | drivers/dma/intel_mid_dma.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c index c4b81387f0c6..3c4333ee1fb7 100644 --- a/drivers/dma/intel_mid_dma.c +++ b/drivers/dma/intel_mid_dma.c @@ -872,7 +872,6 @@ static int mid_setup_dma(struct pci_dev *pdev) { struct middma_device *dma = pci_get_drvdata(pdev); int err, i; - unsigned int irq_level; /* DMA coherent memory pool for DMA descriptor allocations */ dma->dma_pool = pci_pool_create("intel_mid_dma_desc_pool", pdev, @@ -960,7 +959,6 @@ static int mid_setup_dma(struct pci_dev *pdev) /*register irq */ if (dma->pimr_mask) { - irq_level = IRQF_SHARED; pr_debug("MDMA:Requesting irq shared for DMAC1\n"); err = request_irq(pdev->irq, intel_mid_dma_interrupt1, IRQF_SHARED, "INTEL_MID_DMAC1", dma); @@ -968,10 +966,9 @@ static int mid_setup_dma(struct pci_dev *pdev) goto err_irq; } else { dma->intr_mask = 0x03; - irq_level = 0; pr_debug("MDMA:Requesting irq for DMAC2\n"); err = request_irq(pdev->irq, intel_mid_dma_interrupt2, - 0, "INTEL_MID_DMAC2", dma); + IRQF_SHARED, "INTEL_MID_DMAC2", dma); if (0 != err) goto err_irq; } |