diff options
author | Alan Liu <HaoPing.Liu@amd.com> | 2022-10-19 18:15:14 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2022-12-15 12:18:18 -0500 |
commit | 1b11ff764aefc0aa5199ad5ae4c45e591ca3090a (patch) | |
tree | 0bfc33e668153a092d2e5a64dd45d590085db0c0 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | |
parent | 7a18e089eff02f17eaee49fc18641f5d16a8284b (diff) | |
download | linux-1b11ff764aefc0aa5199ad5ae4c45e591ca3090a.tar.gz linux-1b11ff764aefc0aa5199ad5ae4c45e591ca3090a.tar.bz2 linux-1b11ff764aefc0aa5199ad5ae4c45e591ca3090a.zip |
drm/amd/display: Implement multiple secure display
[Why]
Current secure display only work with single display, now make it
work with multiple displays.
[How]
Create secure_display_context for each crtc instance to store its
own Region of Interest (ROI) information.
v2: squash in warning fix (Alex)
Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 38 |
1 files changed, 8 insertions, 30 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 461037a3dd75..a29952cd8f22 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3245,46 +3245,24 @@ DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, */ static int crc_win_update_set(void *data, u64 val) { - struct drm_crtc *new_crtc = data; - struct drm_crtc *old_crtc = NULL; - struct amdgpu_crtc *new_acrtc, *old_acrtc; - struct amdgpu_device *adev = drm_to_adev(new_crtc->dev); - struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; - - if (!crc_rd_wrk) - return 0; + struct drm_crtc *crtc = data; + struct amdgpu_crtc *acrtc; + struct amdgpu_device *adev = drm_to_adev(crtc->dev); if (val) { - new_acrtc = to_amdgpu_crtc(new_crtc); + acrtc = to_amdgpu_crtc(crtc); mutex_lock(&adev->dm.dc_lock); /* PSR may write to OTG CRC window control register, * so close it before starting secure_display. */ - amdgpu_dm_psr_disable(new_acrtc->dm_irq_params.stream); + amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream); spin_lock_irq(&adev_to_drm(adev)->event_lock); - spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); - if (crc_rd_wrk->crtc) { - old_crtc = crc_rd_wrk->crtc; - old_acrtc = to_amdgpu_crtc(old_crtc); - } - if (old_crtc && old_crtc != new_crtc) { - old_acrtc->dm_irq_params.window_param.activated = false; - old_acrtc->dm_irq_params.window_param.update_win = false; - old_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; + acrtc->dm_irq_params.window_param.activated = true; + acrtc->dm_irq_params.window_param.update_win = true; + acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; - new_acrtc->dm_irq_params.window_param.activated = true; - new_acrtc->dm_irq_params.window_param.update_win = true; - new_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; - crc_rd_wrk->crtc = new_crtc; - } else { - new_acrtc->dm_irq_params.window_param.activated = true; - new_acrtc->dm_irq_params.window_param.update_win = true; - new_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; - crc_rd_wrk->crtc = new_crtc; - } - spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); spin_unlock_irq(&adev_to_drm(adev)->event_lock); mutex_unlock(&adev->dm.dc_lock); } |