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| author | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2021-03-15 14:55:24 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-05-19 22:42:00 -0400 |
| commit | cd6d421e3d1ad5926b74091254e345db730e7706 (patch) | |
| tree | a144ed0fbf4c91deff906014364414b3f9fb7519 /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | |
| parent | 8198ace7a074de4dfdc10885ccf081476b50d41b (diff) | |
| download | linux-cd6d421e3d1ad5926b74091254e345db730e7706.tar.gz linux-cd6d421e3d1ad5926b74091254e345db730e7706.tar.bz2 linux-cd6d421e3d1ad5926b74091254e345db730e7706.zip | |
drm/amd/display: Initial DC support for Beige Goby
[Why&How]
Add Beige Goby (DCN303) resource, irq service, & dmub loader.
v2: fix nbio include (Alex)
Signed-off-by: Chris Park <Chris.Park@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index 7fe5a07e2233..3139285bd403 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -142,6 +142,15 @@ SRII(PIXEL_RATE_CNTL, OTG, 3),\ SRII(PIXEL_RATE_CNTL, OTG, 4) +#define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \ + SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ + SRII(PHASE, DP_DTO, 0),\ + SRII(PHASE, DP_DTO, 1),\ + SRII(MODULO, DP_DTO, 0),\ + SRII(MODULO, DP_DTO, 1),\ + SRII(PIXEL_RATE_CNTL, OTG, 0),\ + SRII(PIXEL_RATE_CNTL, OTG, 1) + #endif #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ |