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| author | Hersen Wu <hersenxs.wu@amd.com> | 2018-08-21 09:35:47 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-09-10 22:43:18 -0500 |
| commit | 0e8e4fbf8d8905071c045f2922de55adbe1a6abe (patch) | |
| tree | 628d390bf35e2df39a5d614e215d4b6d92ac9b1b /drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | |
| parent | 86a2da705cc29a3a006c6571cadfa45676150622 (diff) | |
| download | linux-0e8e4fbf8d8905071c045f2922de55adbe1a6abe.tar.gz linux-0e8e4fbf8d8905071c045f2922de55adbe1a6abe.tar.bz2 linux-0e8e4fbf8d8905071c045f2922de55adbe1a6abe.zip | |
drm/amd/display: num of sw i2c/aux engines less than num of connectors
[why]
AMD Stoney reference board, there are only 2 pipes (not include
underlay), and 3 connectors. resource creation, only
2 I2C/AUX engines are created. Within dc_link_aux_transfer, when
pin_data_en =2, refer to enengines[ddc_pin->pin_data->en] = NULL.
NULL point is referred later causing system crash.
[how]
each asic design has fixed number of ddc engines at hw side.
for each ddc engine, create its i2x/aux engine at sw side.
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index b2fb06f37648..465f68655db2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -436,6 +436,7 @@ static const struct resource_caps res_cap = { .num_audio = 7, .num_stream_encoder = 6, .num_pll = 6, + .num_ddc = 6, }; static const struct dc_debug_options debug_defaults = { @@ -1062,6 +1063,12 @@ static bool construct( dm_error( "DC: failed to create output pixel processor!\n"); } + + /* check next valid pipe */ + j++; + } + + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce120_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1077,8 +1084,6 @@ static bool construct( goto res_create_fail; } pool->base.sw_i2cs[i] = NULL; - /* check next valid pipe */ - j++; } /* valid pipe num */ |