diff options
| author | Sung Lee <sung.lee@amd.com> | 2021-01-15 13:53:15 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-02-02 12:09:17 -0500 |
| commit | fc13b7011e8a1d81787f9caf934d97b17b4f4fb5 (patch) | |
| tree | 0cefc9db56feeeb22cae0ca2abebd3531224846f /drivers/gpu/drm/amd/display/dc/dcn21 | |
| parent | aac6d4391a0a354bcb59885ce990ca934563143a (diff) | |
| download | linux-fc13b7011e8a1d81787f9caf934d97b17b4f4fb5.tar.gz linux-fc13b7011e8a1d81787f9caf934d97b17b4f4fb5.tar.bz2 linux-fc13b7011e8a1d81787f9caf934d97b17b4f4fb5.zip | |
drm/amd/display: Add more Clock Sources to DCN2.1
[WHY]
When enabling HDMI on ComboPHY, there are not
enough clock sources to complete display detection.
[HOW]
Initialize more clock sources.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn21')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index b000b43a820d..674376428916 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -906,6 +906,8 @@ enum dcn20_clk_src_array_id { DCN20_CLK_SRC_PLL0, DCN20_CLK_SRC_PLL1, DCN20_CLK_SRC_PLL2, + DCN20_CLK_SRC_PLL3, + DCN20_CLK_SRC_PLL4, DCN20_CLK_SRC_TOTAL_DCN21 }; @@ -2030,6 +2032,14 @@ static bool dcn21_resource_construct( dcn21_clock_source_create(ctx, ctx->dc_bios, CLOCK_SOURCE_COMBO_PHY_PLL2, &clk_src_regs[2], false); + pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = + dcn21_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL3, + &clk_src_regs[3], false); + pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = + dcn21_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL4, + &clk_src_regs[4], false); pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; |