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| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2021-02-17 11:32:10 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-23 23:33:32 -0400 |
| commit | 443dfba02483872384354bc0e62c656e3f82b6a9 (patch) | |
| tree | bc02acaee8c12fb6877b2dda26c06793e7c340ea /drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | |
| parent | 8ee0fea4baf90e43efe2275de208a7809f9985bc (diff) | |
| download | linux-443dfba02483872384354bc0e62c656e3f82b6a9.tar.gz linux-443dfba02483872384354bc0e62c656e3f82b6a9.tar.bz2 linux-443dfba02483872384354bc0e62c656e3f82b6a9.zip | |
drm/amd/display: fix dcn3+ bw validation soc param update sequence
SOC needs to be updated to the WM set A values before validation
happens.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c index 950b9a08084e..0fbdfff87835 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c @@ -1627,6 +1627,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .panel_cntl_create = dcn301_panel_cntl_create, .validate_bandwidth = dcn30_validate_bandwidth, .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, + .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, .add_stream_to_ctx = dcn30_add_stream_to_ctx, |