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authorKarthi Kandasamy <karthi.kandasamy@amd.com>2024-11-20 13:30:11 +0100
committerAlex Deucher <alexander.deucher@amd.com>2025-01-06 14:44:27 -0500
commit080950cbdd8309110eab93b76f0caf53be0d5120 (patch)
tree1fbb808b9b169ae9fd923ffd4bb47239d558b904 /drivers/gpu/drm/amd/display/dc/hubp/dcn401
parente8b19ffea957651b9eab296634115b72f95e86ca (diff)
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drm/amd/display: Update dc_tiling_info union to structure
[WHY] The `dc_tiling_info` union previously did not have a field to specify the active GFX format, assuming only one format would be used per DCN version. from DCN4+, support for switching between different GFX formats is introduced, requiring a way to track which format is currently in use. [HOW] Updated the `dc_tiling_info` union to include a new field that explicitly indicates the currently used GFX format. This allows the system to determine the active GFX format and take the correct programming path accordingly. [Description] The union `dc_tiling_info` has been updated to support multiple GFX formats by adding a new field for identifying the active format. This update ensures that the correct programming path is followed based on the selected format. All references to `dc_tiling_info` in the codebase have been updated to reflect the new structure. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/hubp/dcn401')
-rw-r--r--drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c4
-rw-r--r--drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
index 09f730cfbf8e..d38e3f3a1107 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
@@ -532,7 +532,7 @@ void hubp401_dcc_control(struct hubp *hubp,
void hubp401_program_tiling(
struct dcn20_hubp *hubp2,
- const union dc_tiling_info *info,
+ const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
/* DCSURF_ADDR_CONFIG still shows up in reg spec, but does not need to be programmed for DCN4x
@@ -580,7 +580,7 @@ void hubp401_program_size(
void hubp401_program_surface_config(
struct hubp *hubp,
enum surface_pixel_format format,
- union dc_tiling_info *tiling_info,
+ struct dc_tiling_info *tiling_info,
struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
index 9b200a55bf9d..9e2cf8b5e344 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
@@ -290,7 +290,7 @@ void hubp401_dcc_control(struct hubp *hubp,
void hubp401_program_tiling(
struct dcn20_hubp *hubp2,
- const union dc_tiling_info *info,
+ const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format);
void hubp401_program_size(
@@ -302,7 +302,7 @@ void hubp401_program_size(
void hubp401_program_surface_config(
struct hubp *hubp,
enum surface_pixel_format format,
- union dc_tiling_info *tiling_info,
+ struct dc_tiling_info *tiling_info,
struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,