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| author | Saaem Rizvi <syedsaaem.rizvi@amd.com> | 2023-05-11 15:16:35 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 10:44:17 -0400 |
| commit | 2da3556c8650798606c0d3f2288b2f87c6665a69 (patch) | |
| tree | bb05dd412b840bc46b6772d8e377eaccd42a1acd /drivers/gpu/drm/amd/display/dmub/src | |
| parent | 268182606f26434c5d3ebd0e86efcb0418dec487 (diff) | |
| download | linux-2da3556c8650798606c0d3f2288b2f87c6665a69.tar.gz linux-2da3556c8650798606c0d3f2288b2f87c6665a69.tar.bz2 linux-2da3556c8650798606c0d3f2288b2f87c6665a69.zip | |
drm/amd/display: Trigger DIO FIFO resync on commit streams for DCN32
[WHY and HOW]
Currently, on DCN32 we have an old workaround to resolve a DIO FIFO
speed issue when writing to the OTG DIVIDER register. However, this
workaround is not safe as we should be applying the DIO FIFO rampup
logic when the OTG re disabled along with the encoders. This new
workaround accounts for this. If the workaround sequence is incorrect,
like it is was, there is a chance we might hang. this new
workaround was first implemented in DCN314.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Saaem Rizvi <syedsaaem.rizvi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/src')
0 files changed, 0 insertions, 0 deletions