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| author | Hugo Hu <hugo.hu@amd.com> | 2019-02-27 15:18:08 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-03-20 23:39:48 -0500 |
| commit | 3d5cc272319d6b7bf2e7d8aa9b1c3b0fe3e85b3f (patch) | |
| tree | ef40d2d2d0b87f354b588b236d0ae8bfff142ec7 /drivers/gpu/drm/amd/display/modules/freesync | |
| parent | 8db89b2e39ffe363f27fdd335e35b59c90979ea5 (diff) | |
| download | linux-3d5cc272319d6b7bf2e7d8aa9b1c3b0fe3e85b3f.tar.gz linux-3d5cc272319d6b7bf2e7d8aa9b1c3b0fe3e85b3f.tar.bz2 linux-3d5cc272319d6b7bf2e7d8aa9b1c3b0fe3e85b3f.zip | |
drm/amd/display: Programming correct VRR_EN bit in VTEM structure
[Why]
In HDMI plugfest, MTK report our EMP with VRR_EN bit = 0.
VRR_EN bit is EMP-MD0-bit 0. Currently driver set 1 to bit 3.
[How]
Programming correct VRR_EN bit in EMP-MD0-bit0.
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Reza Amini <Reza.Amini@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync')
| -rw-r--r-- | drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 5f493e9d6bbb..8f6f744fb2be 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -622,9 +622,9 @@ static void build_vrr_vtem_infopacket_data(const struct dc_stream_state *stream, if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || vrr->state == VRR_STATE_ACTIVE_FIXED){ - infopacket->sb[6] |= 0x80; //VRR_EN Bit = 1 + infopacket->sb[6] |= 0x01; //VRR_EN Bit = 1 } else { - infopacket->sb[6] &= 0x7F; //VRR_EN Bit = 0 + infopacket->sb[6] &= 0xFE; //VRR_EN Bit = 0 } if (!stream->timing.vic) { |