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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-09 18:49:46 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-18 22:38:27 +0200 |
| commit | 0fed4ddd18f064d2359b430c6e83ee60dd1f49b1 (patch) | |
| tree | 385c76c16956dab7c03f388e2d13f0b07d12b5fc /drivers/gpu/drm/i915/display/intel_bw.c | |
| parent | 4593e8e064353c4db3c1ad0f774d389af33d31c5 (diff) | |
| download | linux-0fed4ddd18f064d2359b430c6e83ee60dd1f49b1.tar.gz linux-0fed4ddd18f064d2359b430c6e83ee60dd1f49b1.tar.bz2 linux-0fed4ddd18f064d2359b430c6e83ee60dd1f49b1.zip | |
drm/i915: Fix PSF GV point mask when SAGV is not possible
Don't just mask off all the PSF GV points when SAGV gets disabled.
This should in fact cause the Pcode to reject the request since
at least one PSF point must remain enabled at all times.
Cc: stable@vger.kernel.org
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point support")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220309164948.10671-7-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_bw.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_bw.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index ad1564ca7269..adf58c58513b 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -992,7 +992,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) * cause. */ if (!intel_can_enable_sagv(dev_priv, new_bw_state)) { - allowed_points = BIT(max_bw_point); + allowed_points &= ADLS_PSF_PT_MASK; + allowed_points |= BIT(max_bw_point); drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n", max_bw_point); } |