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| author | José Roberto de Souza <jose.souza@intel.com> | 2021-05-24 14:48:03 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-05-25 10:30:26 -0700 |
| commit | b554065cb6fc665bf0dac61cc6e79c73c4e4e21e (patch) | |
| tree | 3aa4c84ce9326ec18dbb8c41359e814a7037dd32 /drivers/gpu/drm/i915/display/intel_bw.c | |
| parent | 8c80332d6735a39f87bb1362c54fa6ede5a844d3 (diff) | |
| download | linux-b554065cb6fc665bf0dac61cc6e79c73c4e4e21e.tar.gz linux-b554065cb6fc665bf0dac61cc6e79c73c4e4e21e.tar.bz2 linux-b554065cb6fc665bf0dac61cc6e79c73c4e4e21e.zip | |
drm/i915: WA for zero memory channel
Commit c457d9cf256e ("drm/i915: Make sure we have enough memory
bandwidth on ICL") assumes that we always have a non-zero
dram_info->channels and uses it as a divisor.
We need num memory channels to be at least 1 for sane bw limits
checking, even when PCode returns 0 or there is a error reading it, so
lets force it to 1 in this case.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210524214805.259692-3-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_bw.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_bw.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 3a1ba52266a7..bfb398f0432e 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -162,7 +162,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel { struct intel_qgv_info qi = {}; bool is_y_tile = true; /* assume y tile may be used */ - int num_channels = dev_priv->dram_info.num_channels; + int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); int deinterleave; int ipqdepth, ipqdepthpch; int dclk_max; |