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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-10-06 23:49:37 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-10-28 21:20:00 +0300 |
| commit | ead3ea12e133416fbd800eedb2fb5d0faf2df431 (patch) | |
| tree | 8009d1e89c8353eca8a65d175c8b9d8442963e78 /drivers/gpu/drm/i915/display/intel_combo_phy.c | |
| parent | 32c2bc89c7420fad2959ee23ef5b6be8b05d2bde (diff) | |
| download | linux-ead3ea12e133416fbd800eedb2fb5d0faf2df431.tar.gz linux-ead3ea12e133416fbd800eedb2fb5d0faf2df431.tar.bz2 linux-ead3ea12e133416fbd800eedb2fb5d0faf2df431.zip | |
drm/i915: Fix icl+ combo phy static lane power down setup
Our lane power down defines already include the necessary shift,
don't shift them a second time.
Fortunately we masked off the correct bits, so we accidentally
left all lanes powered up all the time.
Bits 8-11 where we end up writing our misdirected lane mask are
documented as MBZ, but looks like you can actually write there
so they're not read only bits. No idea what side effect the
bogus register write might have.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4151
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-17-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_combo_phy.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_combo_phy.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 634e8d449457..f628e0542933 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -301,7 +301,7 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); val &= ~PWR_DOWN_LN_MASK; - val |= lane_mask << PWR_DOWN_LN_SHIFT; + val |= lane_mask; intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); } |