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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-05-16 16:56:16 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-05-22 15:49:51 +0300 |
| commit | 9871927034d177aacc7054e30c74e11fcddf8ee1 (patch) | |
| tree | ec97321f523ce9a457fde964ff37009c5c911df8 /drivers/gpu/drm/i915/display/intel_cursor.c | |
| parent | 0ff7639bb1a6299930b7d66214bc6b0a293d8833 (diff) | |
| download | linux-9871927034d177aacc7054e30c74e11fcddf8ee1.tar.gz linux-9871927034d177aacc7054e30c74e11fcddf8ee1.tar.bz2 linux-9871927034d177aacc7054e30c74e11fcddf8ee1.zip | |
drm/i915: Add separate defines for cursor WM/DDB register bits
Make a more thorough split between universal planes vs. cursors
by defining the contents of the cursor WM/DDB registers separately.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cursor.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cursor.c | 34 |
1 files changed, 28 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 7983cbaf83f7..cea0cfed569d 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -24,7 +24,6 @@ #include "intel_psr.h" #include "intel_psr_regs.h" #include "intel_vblank.h" -#include "skl_universal_plane.h" #include "skl_watermark.h" #include "gem/i915_gem_object.h" @@ -559,6 +558,29 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane, } } +static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry) +{ + if (!entry->end) + return 0; + + return CUR_BUF_END(entry->end - 1) | + CUR_BUF_START(entry->start); +} + +static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level) +{ + u32 val = 0; + + if (level->enable) + val |= CUR_WM_EN; + if (level->ignore_lines) + val |= CUR_WM_IGNORE_LINES; + val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks); + val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines); + + return val; +} + static void skl_write_cursor_wm(struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { @@ -572,22 +594,22 @@ static void skl_write_cursor_wm(struct intel_plane *plane, for (level = 0; level < i915->display.wm.num_levels; level++) intel_de_write_fw(i915, CUR_WM(pipe, level), - skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); + skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); intel_de_write_fw(i915, CUR_WM_TRANS(pipe), - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); + skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); if (HAS_HW_SAGV_WM(i915)) { const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; intel_de_write_fw(i915, CUR_WM_SAGV(pipe), - skl_plane_wm_reg_val(&wm->sagv.wm0)); + skl_cursor_wm_reg_val(&wm->sagv.wm0)); intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe), - skl_plane_wm_reg_val(&wm->sagv.trans_wm)); + skl_cursor_wm_reg_val(&wm->sagv.trans_wm)); } intel_de_write_fw(i915, CUR_BUF_CFG(pipe), - skl_plane_ddb_reg_val(ddb)); + skl_cursor_ddb_reg_val(ddb)); } /* TODO: split into noarm+arm pair */ |