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authorKalle Valo <kvalo@kernel.org>2023-01-17 13:36:25 +0200
committerKalle Valo <kvalo@kernel.org>2023-01-17 13:36:25 +0200
commitd0e99511834b6828c960e978d9a8cb6e5731250d (patch)
treee7b062c1f9d28a55083477a1462286a7923a57fd /drivers/gpu/drm/i915/display/intel_dpio_phy.c
parentde7d0ff301fccc75281d7d8eb98c4a47faacf32d (diff)
parent80f8a66dede0a4b4e9e846765a97809c6fe49ce5 (diff)
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Merge wireless into wireless-next
Due to the two cherry picked commits from wireless to wireless-next we have several conflicts in mt76. To avoid any bugs with conflicts merge wireless into wireless-next. 96f134dc1964 wifi: mt76: handle possible mt76_rx_token_consume failures fe13dad8992b wifi: mt76: dma: do not increment queue head if mt76_dma_add_buf fails
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpio_phy.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_dpio_phy.c43
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 8732b8722ed7..7eb7440b3180 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include "i915_reg.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
@@ -655,6 +656,48 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
return mask;
}
+enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
+{
+ switch (dig_port->base.port) {
+ default:
+ MISSING_CASE(dig_port->base.port);
+ fallthrough;
+ case PORT_B:
+ case PORT_D:
+ return DPIO_CH0;
+ case PORT_C:
+ return DPIO_CH1;
+ }
+}
+
+enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
+{
+ switch (dig_port->base.port) {
+ default:
+ MISSING_CASE(dig_port->base.port);
+ fallthrough;
+ case PORT_B:
+ case PORT_C:
+ return DPIO_PHY0;
+ case PORT_D:
+ return DPIO_PHY1;
+ }
+}
+
+enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)
+{
+ switch (pipe) {
+ default:
+ MISSING_CASE(pipe);
+ fallthrough;
+ case PIPE_A:
+ case PIPE_C:
+ return DPIO_CH0;
+ case PIPE_B:
+ return DPIO_CH1;
+ }
+}
+
void chv_set_phy_signal_level(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
u32 deemph_reg_value, u32 margin_reg_value,