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| author | Aditya Swarup <aditya.swarup@intel.com> | 2020-10-14 12:19:30 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2020-10-15 14:14:30 -0700 |
| commit | 049c651b6d93839c74be5cb24708f1d8470ec60d (patch) | |
| tree | 5a2d1f649f44a710d5378eef4508f55425dc8ce8 /drivers/gpu/drm/i915/display/intel_dpll_mgr.h | |
| parent | 240abb3c76ff4b469f91a753adb8426b77cab914 (diff) | |
| download | linux-049c651b6d93839c74be5cb24708f1d8470ec60d.tar.gz linux-049c651b6d93839c74be5cb24708f1d8470ec60d.tar.bz2 linux-049c651b6d93839c74be5cb24708f1d8470ec60d.zip | |
drm/i915/dg1: Add DPLL macros for DG1
DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDI-TC1/DDI-TC2.
Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.
Bspec: 50288, 50299
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-4-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll_mgr.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 5d9a2bc371e7..205542fb8dc7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -154,6 +154,23 @@ enum intel_dpll_id { * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) */ DPLL_ID_TGL_MGPLL6 = 8, + + /** + * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0 + */ + DPLL_ID_DG1_DPLL0 = 0, + /** + * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1 + */ + DPLL_ID_DG1_DPLL1 = 1, + /** + * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2 + */ + DPLL_ID_DG1_DPLL2 = 2, + /** + * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3 + */ + DPLL_ID_DG1_DPLL3 = 3, }; #define I915_NUM_PLLS 9 |