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| author | Jani Nikula <jani.nikula@intel.com> | 2022-08-30 13:28:00 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2022-08-31 18:09:20 +0300 |
| commit | 6d737d9bff5fe98e01bedb39ab9f5be3a39b5ddf (patch) | |
| tree | f17710e40ac99954773784ddc86ab4160295e7aa /drivers/gpu/drm/i915/display/intel_gmbus_regs.h | |
| parent | 4567084c305154b5abd427f568132432c41f13ef (diff) | |
| download | linux-6d737d9bff5fe98e01bedb39ab9f5be3a39b5ddf.tar.gz linux-6d737d9bff5fe98e01bedb39ab9f5be3a39b5ddf.tar.bz2 linux-6d737d9bff5fe98e01bedb39ab9f5be3a39b5ddf.zip | |
drm/i915/gmbus: stop using implicit dev_priv in register definitions
Since the beginning of time, we've implicitly assumed dev_priv is
present as a local variable in many places. We've gone a long way in
removing many of them, but the register macro definitions are the last
holdout. Remove them from the gmbus macros.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a4f482c1f523d7225420f8386f1eea6d639db843.1661855191.git.jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_gmbus_regs.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_gmbus_regs.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus_regs.h b/drivers/gpu/drm/i915/display/intel_gmbus_regs.h index 1d58925df856..53aacbda983c 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus_regs.h +++ b/drivers/gpu/drm/i915/display/intel_gmbus_regs.h @@ -10,7 +10,7 @@ #define GMBUS_MMIO_BASE(__i915) ((__i915)->display.gmbus.mmio_base) -#define GPIO(gpio) _MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5010 + 4 * (gpio)) +#define GPIO(__i915, gpio) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5010 + 4 * (gpio)) #define GPIO_CLOCK_DIR_MASK (1 << 0) #define GPIO_CLOCK_DIR_IN (0 << 1) #define GPIO_CLOCK_DIR_OUT (1 << 1) @@ -27,7 +27,7 @@ #define GPIO_DATA_PULLUP_DISABLE (1 << 13) /* clock/port select */ -#define GMBUS0 _MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5100) +#define GMBUS0(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5100) #define GMBUS_AKSV_SELECT (1 << 11) #define GMBUS_RATE_100KHZ (0 << 8) #define GMBUS_RATE_50KHZ (1 << 8) @@ -37,7 +37,7 @@ #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) /* command/status */ -#define GMBUS1 _MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5104) +#define GMBUS1(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5104) #define GMBUS_SW_CLR_INT (1 << 31) #define GMBUS_SW_RDY (1 << 30) #define GMBUS_ENT (1 << 29) /* enable timeout */ @@ -54,7 +54,7 @@ #define GMBUS_SLAVE_WRITE (0 << 0) /* status */ -#define GMBUS2 _MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5108) +#define GMBUS2(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5108) #define GMBUS_INUSE (1 << 15) #define GMBUS_HW_WAIT_PHASE (1 << 14) #define GMBUS_STALL_TIMEOUT (1 << 13) @@ -64,10 +64,10 @@ #define GMBUS_ACTIVE (1 << 9) /* data buffer bytes 3-0 */ -#define GMBUS3 _MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x510c) +#define GMBUS3(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x510c) /* interrupt mask (Pineview+) */ -#define GMBUS4 _MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5110) +#define GMBUS4(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5110) #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) #define GMBUS_NAK_EN (1 << 3) #define GMBUS_IDLE_EN (1 << 2) @@ -75,7 +75,7 @@ #define GMBUS_HW_RDY_EN (1 << 0) /* byte index */ -#define GMBUS5 _MMIO(GMBUS_MMIO_BASE(dev_priv) + 0x5120) +#define GMBUS5(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5120) #define GMBUS_2BYTE_INDEX_EN (1 << 31) #endif /* __INTEL_GMBUS_REGS_H__ */ |