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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-12-01 17:25:39 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-12-03 12:49:02 +0200 |
| commit | f84b336a2ff7473a7c6c15eff6c4ec50aee476a3 (patch) | |
| tree | 172b441ca18941d3c60706b10a9f85e3fc570760 /drivers/gpu/drm/i915/display/skl_universal_plane.c | |
| parent | 15162c5a36abbf051f957ee8114185b899c6975a (diff) | |
| download | linux-f84b336a2ff7473a7c6c15eff6c4ec50aee476a3.tar.gz linux-f84b336a2ff7473a7c6c15eff6c4ec50aee476a3.tar.bz2 linux-f84b336a2ff7473a7c6c15eff6c4ec50aee476a3.zip | |
drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio
Let's just stick to 32bit mmio accesses so we can get rid
of the bare "uncore" reg access in display code. The register
are defined as 32bit in the spec anyway.
We could define a 64bit "de" variant I suppose, but doesn't
really make much sense just for this one case, and when we
start to use the DSB for this stuff we'd also need another
64bit variant for that. Just easier to do 32bit always.
While at it we can reorder stuff a bit so that we write the
registers in order of increasing offset (more or less).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-2-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/skl_universal_plane.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index a8d1617053f8..679815b138cc 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1057,6 +1057,13 @@ skl_program_plane_noarm(struct intel_plane *plane, intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); + if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) { + intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0), + lower_32_bits(plane_state->ccval)); + intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1), + upper_32_bits(plane_state->ccval)); + } + if (icl_is_hdr_plane(dev_priv, plane_id)) intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl); @@ -1064,10 +1071,6 @@ skl_program_plane_noarm(struct intel_plane *plane, if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) icl_program_input_csc(plane, crtc_state, plane_state); - if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) - intel_uncore_write64_fw(&dev_priv->uncore, - PLANE_CC_VAL(pipe, plane_id), plane_state->ccval); - skl_write_plane_wm(plane, crtc_state); intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane); |