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| author | Matt Roper <matthew.d.roper@intel.com> | 2022-01-27 15:43:31 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-02-02 07:52:23 -0800 |
| commit | 7d296f369d38e12b1f9c552d8635eb0caef71095 (patch) | |
| tree | 0a13f8b47924492bf03f1e290a43cc43830ff1a4 /drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | |
| parent | 66a19a3a0e2d200121f30a48d13b80532582f1a5 (diff) | |
| download | linux-7d296f369d38e12b1f9c552d8635eb0caef71095.tar.gz linux-7d296f369d38e12b1f9c552d8635eb0caef71095.tar.bz2 linux-7d296f369d38e12b1f9c552d8635eb0caef71095.zip | |
drm/i915: Parameterize R_PWR_CLK_STATE register definition
At the moment we only use R_PWR_CLK_STATE in the context of the RCS
engine, but upcoming support for compute engines will start using
instances relative to the CCS engine base offsets. Let's parameterize
the register and move it to the engine reg header.
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220127234334.4016964-4-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 3f41fe5ec9d4..7d327ffd0464 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -8,6 +8,7 @@ #include "gem/i915_gem_pm.h" #include "gt/intel_engine_pm.h" +#include "gt/intel_engine_regs.h" #include "gt/intel_gt.h" #include "gt/intel_gt_requests.h" #include "gt/intel_reset.h" @@ -894,7 +895,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v return PTR_ERR(cmd); *cmd++ = MI_STORE_REGISTER_MEM_GEN8; - *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE); + *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE)); *cmd++ = lower_32_bits(vma->node.start); *cmd++ = upper_32_bits(vma->node.start); *cmd = MI_BATCH_BUFFER_END; |