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authorStuart Summers <stuart.summers@intel.com>2019-08-23 09:02:59 -0700
committerChris Wilson <chris@chris-wilson.co.uk>2019-08-23 19:14:21 +0100
commit7a200aad1127e98cbf4da9685f652899598fe357 (patch)
tree503a4cf958696effa2b60611fdafc705ceee5e07 /drivers/gpu/drm/i915/gt/intel_sseu.h
parent8b355db99cfbdaea848e05c288d6d80c391f0b13 (diff)
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drm/i915: Add subslice stride runtime parameter
Add a new parameter, ss_stride, to the runtime info structure. This is used to mirror the userspace concept of subslice stride, which is a range of subslices per slice. This patch simply adds the definition and updates usage in the QUERY_TOPOLOGY_INFO handler. v2: Add GEM_BUG_ON to make sure ss_stride is valid Signed-off-by: Stuart Summers <stuart.summers@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190823160307.180813-4-stuart.summers@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_sseu.h')
-rw-r--r--drivers/gpu/drm/i915/gt/intel_sseu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 64e47dad07be..8b8b562ff773 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -15,6 +15,7 @@ struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
struct sseu_dev_info {
u8 slice_mask;
@@ -33,6 +34,8 @@ struct sseu_dev_info {
u8 max_subslices;
u8 max_eus_per_subslice;
+ u8 ss_stride;
+
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
* subslice.