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authorChris Wilson <chris@chris-wilson.co.uk>2019-08-08 12:06:11 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2019-08-08 15:45:34 +0100
commit387758298bfdec9fbb74406207eb648bb6391670 (patch)
tree8e33bbf7b4b3c6f95db7f01a06656fb745cedeec /drivers/gpu/drm/i915/gvt
parentca883c304f54a5b2fc83c2729691e9eae3a1226e (diff)
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drm/i915: Allocate kernel_contexts directly
Ignore the central i915->kernel_context for allocating an engine, as that GEM context is being phased out. For internal clients, we just need the per-engine logical state, so allocate it at the point of use. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190808110612.23539-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/gvt')
-rw-r--r--drivers/gpu/drm/i915/gvt/scheduler.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 431fd427c49c..0a0a17bea540 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1229,7 +1229,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
INIT_LIST_HEAD(&s->workload_q_head[i]);
s->shadow[i] = ERR_PTR(-EINVAL);
- ce = i915_gem_context_get_engine(ctx, i);
+ ce = intel_context_create(ctx, engine);
if (IS_ERR(ce)) {
ret = PTR_ERR(ce);
goto out_shadow_ctx;
@@ -1270,6 +1270,7 @@ out_shadow_ctx:
break;
intel_context_unpin(s->shadow[i]);
+ intel_context_put(s->shadow[i]);
}
i915_gem_context_put(ctx);
return ret;