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| author | Michel Thierry <michel.thierry@intel.com> | 2019-08-17 02:38:24 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2019-08-20 12:48:57 -0700 |
| commit | 465242ee36ebd5a4f31df64692c634f402c8f2d9 (patch) | |
| tree | 4cddfb879fdf4fde20387f24b1e91865a5ef83ce /drivers/gpu/drm/i915/intel_device_info.c | |
| parent | ea6591b4dadba6f4cac8a7964ce8181770f035e1 (diff) | |
| download | linux-465242ee36ebd5a4f31df64692c634f402c8f2d9.tar.gz linux-465242ee36ebd5a4f31df64692c634f402c8f2d9.tar.bz2 linux-465242ee36ebd5a4f31df64692c634f402c8f2d9.zip | |
drm/i915/tgl: add support for reading the timestamp frequency
There are no changes with respect to GEN11, which Paulo wrote.
This gets rid of the "Missing switch case in read_timestamp_frequency"
message at boot for Tiger Lake.
[ Lucas: BSpec: 10742 and 9024, but there's a mismatch on the values.
Let's say a glitch in the spec. Tested locally and it works. ]
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190817093902.2171-3-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_device_info.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_device_info.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 2a39b52c3582..d0ed44d33484 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -716,7 +716,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) } return freq; - } else if (INTEL_GEN(dev_priv) <= 11) { + } else if (INTEL_GEN(dev_priv) <= 12) { u32 ctc_reg = I915_READ(CTC_MODE); u32 freq = 0; |