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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-05-28 16:42:53 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-05-30 22:51:20 +0200 |
| commit | 0dd87d2084fc9e1f663d3a2c24f0e3f94b7f20e4 (patch) | |
| tree | e0f707a46be9b2ef7b6aea0464b51ca7393e250f /drivers/gpu/drm/i915/intel_hdmi.c | |
| parent | 5cde2a62e8adf12b02e47cf15630e87d4ba8ad5e (diff) | |
| download | linux-0dd87d2084fc9e1f663d3a2c24f0e3f94b7f20e4.tar.gz linux-0dd87d2084fc9e1f663d3a2c24f0e3f94b7f20e4.tar.bz2 linux-0dd87d2084fc9e1f663d3a2c24f0e3f94b7f20e4.zip | |
drm/i915: explicitly disable the DIPs we're not using
From this point on, the 'set_infoframe' functions always set the DIP
registers to a known state, so anything done will always be undone at
the modeset.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_hdmi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 614d83fb6738..620b0dba9e7a 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -350,6 +350,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder, } val |= VIDEO_DIP_ENABLE; + val &= ~VIDEO_DIP_ENABLE_VENDOR; I915_WRITE(reg, val); @@ -393,6 +394,8 @@ static void ibx_set_infoframes(struct drm_encoder *encoder, } val |= VIDEO_DIP_ENABLE; + val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | + VIDEO_DIP_ENABLE_GCP); I915_WRITE(reg, val); @@ -422,6 +425,8 @@ static void cpt_set_infoframes(struct drm_encoder *encoder, /* Set both together, unset both together: see the spec. */ val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; + val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | + VIDEO_DIP_ENABLE_GCP); I915_WRITE(reg, val); @@ -450,6 +455,8 @@ static void vlv_set_infoframes(struct drm_encoder *encoder, } val |= VIDEO_DIP_ENABLE; + val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | + VIDEO_DIP_ENABLE_GCP); I915_WRITE(reg, val); @@ -464,12 +471,18 @@ static void hsw_set_infoframes(struct drm_encoder *encoder, struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); + u32 val = I915_READ(reg); if (!intel_hdmi->has_hdmi_sink) { I915_WRITE(reg, 0); return; } + val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | + VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); + + I915_WRITE(reg, val); + intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); intel_hdmi_set_spd_infoframe(encoder); } |