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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-06-14 11:04:50 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-06-18 18:41:47 +0200 |
| commit | e3f33d46fd917747e966f8e6d25f2940223ad1ee (patch) | |
| tree | 22cc564065251dfaed46c55d76f5f8d82c5386f4 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 6edaa7fcf287b92fb231a9e23cd6b5b0fc3dddb2 (diff) | |
| download | linux-e3f33d46fd917747e966f8e6d25f2940223ad1ee.tar.gz linux-e3f33d46fd917747e966f8e6d25f2940223ad1ee.tar.bz2 linux-e3f33d46fd917747e966f8e6d25f2940223ad1ee.zip | |
drm/i915: add L3 bank clock gating disable on VLV
Prevents a possible hang: WaDisableL3Bank2xClockGate.
v2: only apply to VLV, IVB doesn't need this anymore
References: https://bugs.freedesktop.org/show_bug.cgi?id=50245
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 47c1a3e9b4af..17c16f026244 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3517,6 +3517,8 @@ static void valleyview_init_clock_gating(struct drm_device *dev) GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); + I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); + for_each_pipe(pipe) { I915_WRITE(DSPCNTR(pipe), I915_READ(DSPCNTR(pipe)) | |