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authorNick Hoath <nicholas.hoath@intel.com>2015-05-07 14:15:37 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-05-08 13:04:16 +0200
commit16be17af2ae9fd1544b5d0c58b4facf198031cb8 (patch)
tree9b99721b6eb2eb3cc5138def114600b80159585d /drivers/gpu/drm/i915/intel_ringbuffer.c
parent27160c96e1897c541fa72a86fcfa2f2f67f73876 (diff)
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drm/i915/bxt: Mark WaCcsTlbPrefetchDisable as for Broxton also.
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e74feedd6bee..9b96ed7de9bb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -957,7 +957,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
/* WaDisablePartialResolveInVc:skl,bxt */
WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
- /* WaCcsTlbPrefetchDisable:skl */
+ /* WaCcsTlbPrefetchDisable:skl,bxt */
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE);