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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2021-05-15 22:09:08 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-06-23 07:33:54 -0700 |
| commit | dfa35bac99305a7af03147516055fcc93d9d277a (patch) | |
| tree | 0cf5f46610c9e3ed03769dbc55cdd8c26bcbbb45 /drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | |
| parent | 6f94be582d6faa9e027c026ccc684a0dad398717 (diff) | |
| download | linux-dfa35bac99305a7af03147516055fcc93d9d277a.tar.gz linux-dfa35bac99305a7af03147516055fcc93d9d277a.tar.bz2 linux-dfa35bac99305a7af03147516055fcc93d9d277a.zip | |
drm/msm/dpu: use struct dpu_hw_merge_3d in dpu_hw_pingpong
Use struct dpu_hw_merge_3d pointer in struct dpu_hw_pingpong rather
than using struct dpu_hw_blk. This is the only user of dpu_hw_blk.id,
which will be cleaned in the next patch.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210515190909.1809050-4-dmitry.baryshkov@linaro.org
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 391b13b99c01..185379b18572 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -285,7 +285,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( intf_cfg.stream_sel = 0; /* Don't care value for video mode */ intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); if (phys_enc->hw_pp->merge_3d) - intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id; + intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, @@ -299,11 +299,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine( true, phys_enc->hw_pp->idx); - if (phys_enc->hw_pp->merge_3d) { - struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d); - - merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d); - } + if (phys_enc->hw_pp->merge_3d) + phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); @@ -448,7 +445,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx); if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d) - ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id); + ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); skip_flush: DPU_DEBUG_VIDENC(phys_enc, |