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| author | Ben Skeggs <bskeggs@redhat.com> | 2023-09-19 06:21:47 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2023-10-31 15:08:18 +1000 |
| commit | 08ab88f5a033c67625272eda99de4d245809e0f6 (patch) | |
| tree | 94765c5eea3655cad7f4f5da5363ae17a651b711 /drivers/gpu/drm/nouveau/include | |
| parent | 142cd60243cac1dfa18d3714ed4dd0cdc3786180 (diff) | |
| download | linux-08ab88f5a033c67625272eda99de4d245809e0f6.tar.gz linux-08ab88f5a033c67625272eda99de4d245809e0f6.tar.bz2 linux-08ab88f5a033c67625272eda99de4d245809e0f6.zip | |
drm/nouveau/nvenc/r535: initial support
Adds support for allocating VIDEO_ENCODER classes from RM.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-43-skeggsb@gmail.com
Diffstat (limited to 'drivers/gpu/drm/nouveau/include')
4 files changed, 17 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 17a8867648b9..86648c5d0dba 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -231,6 +231,10 @@ #define AMPERE_DMA_COPY_A 0x0000c6b5 #define AMPERE_DMA_COPY_B 0x0000c7b5 +#define NVC4B7_VIDEO_ENCODER 0x0000c4b7 +#define NVC7B7_VIDEO_ENCODER 0x0000c7b7 +#define NVC9B7_VIDEO_ENCODER 0x0000c9b7 + #define FERMI_DECOMPRESS 0x000090b8 #define NV50_COMPUTE 0x000050c0 diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h index 1f6eef13f872..018c58fc32ba 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h @@ -13,4 +13,6 @@ struct nvkm_nvenc { int gm107_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **); int tu102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **); +int ga102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **); +int ad102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/nvos.h b/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/nvos.h index 5c1cad9bc5db..61b98109a1c8 100644 --- a/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/nvos.h +++ b/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/nvos.h @@ -114,6 +114,13 @@ typedef struct typedef struct { + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of MSENC? + NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2 +} NV_MSENC_ALLOCATION_PARAMETERS; + +typedef struct +{ NvU32 index; NvV32 flags; NvU64 vaSize NV_ALIGN_BYTES(8); diff --git a/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gpu/intr/engine_idx.h b/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gpu/intr/engine_idx.h index b5cc77ab05a3..5ed292000036 100644 --- a/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gpu/intr/engine_idx.h +++ b/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gpu/intr/engine_idx.h @@ -32,6 +32,10 @@ #define MC_ENGINE_IDX_CE9 24 +#define MC_ENGINE_IDX_MSENC 38 + +#define MC_ENGINE_IDX_MSENC2 40 + #define MC_ENGINE_IDX_GSP 49 #define MC_ENGINE_IDX_BSP 64 |