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| author | Ben Skeggs <bskeggs@redhat.com> | 2012-05-01 20:48:08 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2012-05-24 16:56:11 +1000 |
| commit | c420b2dc8dc3cdd507214f4df5c5f96f08812cbe (patch) | |
| tree | 6dca9f0aba3de22a2bda5fe647d6945d4f4e986e /drivers/gpu/drm/nouveau/nv10_graph.c | |
| parent | a226c32a386bca0426e500954b79e3fd46afc0d9 (diff) | |
| download | linux-c420b2dc8dc3cdd507214f4df5c5f96f08812cbe.tar.gz linux-c420b2dc8dc3cdd507214f4df5c5f96f08812cbe.tar.bz2 linux-c420b2dc8dc3cdd507214f4df5c5f96f08812cbe.zip | |
drm/nouveau/fifo: turn all fifo modules into engine modules
Been tested on each major revision that's relevant here, but I'm sure there
are still bugs waiting to be ironed out.
This is a *very* invasive change.
There's a couple of pieces left that I don't like much (eg. other engines
using fifo_priv for the channel count), but that's an artefact of there
being a master channel list still. This is changing, slowly.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv10_graph.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv10_graph.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c index 10c0eb5d4233..fb1d88a951de 100644 --- a/drivers/gpu/drm/nouveau/nv10_graph.c +++ b/drivers/gpu/drm/nouveau/nv10_graph.c @@ -759,7 +759,6 @@ static int nv10_graph_unload_context(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; struct nouveau_channel *chan; struct graph_state *ctx; uint32_t tmp; @@ -782,7 +781,7 @@ nv10_graph_unload_context(struct drm_device *dev) nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000); tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff; - tmp |= (pfifo->channels - 1) << 24; + tmp |= 31 << 24; nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp); return 0; } @@ -822,12 +821,12 @@ struct nouveau_channel * nv10_graph_channel(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int chid = dev_priv->engine.fifo.channels; + int chid = 31; if (nv_rd32(dev, NV10_PGRAPH_CTX_CONTROL) & 0x00010000) chid = nv_rd32(dev, NV10_PGRAPH_CTX_USER) >> 24; - if (chid >= dev_priv->engine.fifo.channels) + if (chid >= 31) return NULL; return dev_priv->channels.ptr[chid]; @@ -948,7 +947,7 @@ nv10_graph_init(struct drm_device *dev, int engine) nv_wr32(dev, NV10_PGRAPH_STATE, 0xFFFFFFFF); tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff; - tmp |= (dev_priv->engine.fifo.channels - 1) << 24; + tmp |= 31 << 24; nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp); nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); |