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| author | Vince Hsu <vinceh@nvidia.com> | 2015-11-16 15:38:30 +0800 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2016-01-11 11:17:40 +1000 |
| commit | da4ee13cd5755a347f16e80e0a8583478c3fef5b (patch) | |
| tree | 75d5aa1c379e56a233befe8bc3bfa728ec553ca1 /drivers/gpu/drm/nouveau | |
| parent | 864d55f4074885705768df01a2f56b0018eef191 (diff) | |
| download | linux-da4ee13cd5755a347f16e80e0a8583478c3fef5b.tar.gz linux-da4ee13cd5755a347f16e80e0a8583478c3fef5b.tar.bz2 linux-da4ee13cd5755a347f16e80e0a8583478c3fef5b.zip | |
drm/nouveau/fifo/gk104: fix engine status register offset
The offset should be 8 on Kepler and later.
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 8d5db6d5a558..4fcd147d43c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -196,7 +196,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) spin_lock_irqsave(&fifo->base.lock, flags); for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) { - u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); + u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); u32 busy = (stat & 0x80000000); u32 next = (stat & 0x07ff0000) >> 16; u32 chsw = (stat & 0x00008000); |