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| author | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2023-01-09 16:02:10 +0200 |
|---|---|---|
| committer | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2023-01-09 16:04:23 +0200 |
| commit | a6fd6f94d36122d8962ba8a24194299a6bb1ecc1 (patch) | |
| tree | 23ba7200bb529a24aab7402ff264d49fb0eaa38c /drivers/gpu | |
| parent | 7e095a4ca32a7169d7c9cce16318b532c85bb39b (diff) | |
| download | linux-a6fd6f94d36122d8962ba8a24194299a6bb1ecc1.tar.gz linux-a6fd6f94d36122d8962ba8a24194299a6bb1ecc1.tar.bz2 linux-a6fd6f94d36122d8962ba8a24194299a6bb1ecc1.zip | |
drm/i915: Fix timeslots argument for DP DSC SST case
We now accept timeslots param exactly how the variable
sounds: amount of timeslots, but not ratio timeslots/64.
So for SST case(when we have all timeslots for use), it
should be 64, but not 1.
This caused some issues in the tests.
v2: Fixed comments
References: https://gitlab.freedesktop.org/drm/intel/-/issues/6860
Fixes: 52f14682ac4d ("drm/i915: Bpp/timeslot calculation fixes for DP MST DSC")
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230109140210.25822-1-stanislav.lisovskiy@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index bf80f296a8fd..30c55f980014 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -713,9 +713,9 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, /* * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* - * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP) - * for SST -> TimeSlotsPerMTP is 1, - * for MST -> TimeSlotsPerMTP has to be calculated + * (LinkSymbolClock)* 8 * (TimeSlots / 64) + * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) + * for MST -> TimeSlots has to be calculated, based on mode requirements */ bits_per_pixel = DIV_ROUND_UP((link_clock * lane_count) * timeslots, intel_dp_mode_to_fec_clock(mode_clock) * 8); @@ -1685,7 +1685,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, str_yes_no(ret), str_yes_no(joiner_needs_dsc), str_yes_no(intel_dp->force_dsc_en)); ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, - conn_state, &limits, 1, true); + conn_state, &limits, 64, true); if (ret < 0) return ret; } |