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authorJonathan Cameron <Jonathan.Cameron@huawei.com>2022-05-08 18:56:37 +0100
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2022-06-14 11:53:16 +0100
commit69e51448ddfb9062efdf83e2d3179498e0aeb293 (patch)
tree266ff2afa37afcfeb527702d0a6349d335a58745 /drivers/iio/dac
parent8482468b30bdb16d4a764f995d7a63d94fa0cf40 (diff)
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iio: dac: ad7303: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: f83478240e74 ("iio:dac: Add support for the AD7303") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-58-jic23@kernel.org
Diffstat (limited to 'drivers/iio/dac')
-rw-r--r--drivers/iio/dac/ad7303.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/iio/dac/ad7303.c b/drivers/iio/dac/ad7303.c
index 03edf046dec6..bff6bf697d9c 100644
--- a/drivers/iio/dac/ad7303.c
+++ b/drivers/iio/dac/ad7303.c
@@ -44,10 +44,10 @@ struct ad7303_state {
struct mutex lock;
/*
- * DMA (thus cache coherency maintenance) requires the
+ * DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
- __be16 data ____cacheline_aligned;
+ __be16 data __aligned(IIO_DMA_MINALIGN);
};
static int ad7303_write(struct ad7303_state *st, unsigned int chan,