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| author | Haoyue Xu <xuhaoyue1@hisilicon.com> | 2022-07-14 21:43:53 +0800 |
|---|---|---|
| committer | Leon Romanovsky <leonro@nvidia.com> | 2022-07-18 14:16:40 +0300 |
| commit | 2de949abd6a539fac4b2c89a560e4ae505b6fb52 (patch) | |
| tree | 750729a7df65e78b5b811272790fb8616aca9643 /drivers/infiniband/hw/hns/hns_roce_device.h | |
| parent | 75e4e716f7089558fda4ddc660fa8dbdec4eb1d3 (diff) | |
| download | linux-2de949abd6a539fac4b2c89a560e4ae505b6fb52.tar.gz linux-2de949abd6a539fac4b2c89a560e4ae505b6fb52.tar.bz2 linux-2de949abd6a539fac4b2c89a560e4ae505b6fb52.zip | |
RDMA/hns: Recover 1bit-ECC error of RAM on chip
Since ECC memory maintains a memory system immune to single-bit errors,
add support for correcting the 1bit-ECC error, which prevents a 1bit-ECC
error become an uncorrected type error. When a 1bit-ECC error happens in
the internal ram of the ROCE engine, such as the QPC table, as a 1bit-ECC
error caused by reading, the ROCE engine only corrects those 1bit ECC
errors by writing.
Link: https://lore.kernel.org/r/20220714134353.16700-6-liangwenpeng@huawei.com
Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com>
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Diffstat (limited to 'drivers/infiniband/hw/hns/hns_roce_device.h')
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_device.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 2855e9ad4b32..f848eedc6a23 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -959,6 +959,7 @@ struct hns_roce_dev { const struct hns_roce_hw *hw; void *priv; struct workqueue_struct *irq_workq; + struct work_struct ecc_work; const struct hns_roce_dfx_hw *dfx; u32 func_num; u32 is_vf; |