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| author | Robin Murphy <robin.murphy@arm.com> | 2019-10-25 19:08:38 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-01-10 15:52:24 +0000 |
| commit | fb485eb18e632ff1071662122b9d9b7d40c23c73 (patch) | |
| tree | d834505d27be2ba860fe327fa1b004ca3aa42c3a /drivers/iommu/io-pgtable-arm-v7s.c | |
| parent | 6f932ad369a3c3f853ffc5d93de9a73420e862b1 (diff) | |
| download | linux-fb485eb18e632ff1071662122b9d9b7d40c23c73.tar.gz linux-fb485eb18e632ff1071662122b9d9b7d40c23c73.tar.bz2 linux-fb485eb18e632ff1071662122b9d9b7d40c23c73.zip | |
iommu/io-pgtable-arm: Rationalise TCR handling
Although it's conceptually nice for the io_pgtable_cfg to provide a
standard VMSA TCR value, the reality is that no VMSA-compliant IOMMU
looks exactly like an Arm CPU, and they all have various other TCR
controls which io-pgtable can't be expected to understand. Thus since
there is an expectation that drivers will have to add to the given TCR
value anyway, let's strip it down to just the essentials that are
directly relevant to io-pgtable's inner workings - namely the various
sizes and the walk attributes.
Tested-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
[will: Add missing include of bitfield.h]
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/iommu/io-pgtable-arm-v7s.c')
| -rw-r--r-- | drivers/iommu/io-pgtable-arm-v7s.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c index 697ffffe34df..4272fe4e17f4 100644 --- a/drivers/iommu/io-pgtable-arm-v7s.c +++ b/drivers/iommu/io-pgtable-arm-v7s.c @@ -149,8 +149,6 @@ #define ARM_V7S_TTBR_IRGN_ATTR(attr) \ ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1)) -#define ARM_V7S_TCR_PD1 BIT(5) - #ifdef CONFIG_ZONE_DMA32 #define ARM_V7S_TABLE_GFP_DMA GFP_DMA32 #define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA32 @@ -798,8 +796,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, */ cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M; - /* TCR: T0SZ=0, disable TTBR1 */ - cfg->arm_v7s_cfg.tcr = ARM_V7S_TCR_PD1; + /* TCR: T0SZ=0, EAE=0 (if applicable) */ + cfg->arm_v7s_cfg.tcr = 0; /* * TEX remap: the indices used map to the closest equivalent types |