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| author | Chao Hao <chao.hao@mediatek.com> | 2020-07-03 12:41:24 +0800 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2020-07-10 16:13:11 +0200 |
| commit | 35c1b48d27dac486835435e703749236b14dcd8f (patch) | |
| tree | 9f2520ae0d9d6a65dc6a176a5d62a1ffcb6d41a7 /drivers/iommu/mtk_iommu.h | |
| parent | 37276e00da7d3a0d643d325aef81b7283fe23010 (diff) | |
| download | linux-35c1b48d27dac486835435e703749236b14dcd8f.tar.gz linux-35c1b48d27dac486835435e703749236b14dcd8f.tar.bz2 linux-35c1b48d27dac486835435e703749236b14dcd8f.zip | |
iommu/mediatek: Add REG_MMU_WR_LEN_CTRL register definition
Some platforms(ex: mt6779) need to improve performance by setting
REG_MMU_WR_LEN_CTRL register. And we can use WR_THROT_EN macro to control
whether we need to set the register. If the register uses default value,
iommu will send command to EMI without restriction, when the number of
commands become more and more, it will drop the EMI performance. So when
more than ten_commands(default value) don't be handled for EMI, iommu will
stop send command to EMI for keeping EMI's performace by enabling write
throttling mechanism(bit[5][21]=0) in MMU_WR_LEN_CTRL register.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20200703044127.27438-8-chao.hao@mediatek.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu/mtk_iommu.h')
| -rw-r--r-- | drivers/iommu/mtk_iommu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 46d0d47b22e1..31edd05e2eb1 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -31,6 +31,7 @@ struct mtk_iommu_suspend_reg { u32 int_main_control; u32 ivrp_paddr; u32 vld_pa_rng; + u32 wr_len_ctrl; }; enum mtk_iommu_plat { |