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authorKonrad Dybcio <konrad.dybcio@linaro.org>2023-11-27 16:52:13 +0100
committerThomas Gleixner <tglx@linutronix.de>2023-12-12 15:40:42 +0100
commit221b110d87c2d3ea113ad784b2c6505726a3e157 (patch)
treee554fdbd265bc1ed84851cedcb1217bc059eea66 /drivers/irqchip
parentca596295f4c9ec803d3379635ad175897993f121 (diff)
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irqchip/qcom-mpm: Support passing a slice of SRAM as reg space
The MPM hardware is accessible from the ARM CPUs through a shared memory region (RPM MSG RAM) which is also concurrently accessed by other kinds of cores on the system like modem, ADSP etc. Modeling this relation in a (somewhat) sane manner in the device tree requires to - either present the MPM as a child of said memory region, which makes little sense, as a mapped memory carveout is not a bus. - define nodes which bleed their register spaces into one another - or passing their slice of the MSG RAM through a property Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as register space for the MPM interrupt controller. The current way of using 'reg' is preserved for backwards compatibility reasons. [ tglx: Massaged changelog ] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20230328-topic-msgram_mpm-v7-2-6ee2bfeaac2c@linaro.org
Diffstat (limited to 'drivers/irqchip')
-rw-r--r--drivers/irqchip/irq-qcom-mpm.c26
1 files changed, 23 insertions, 3 deletions
diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c
index 7124565234a5..cda5838d2232 100644
--- a/drivers/irqchip/irq-qcom-mpm.c
+++ b/drivers/irqchip/irq-qcom-mpm.c
@@ -14,6 +14,7 @@
#include <linux/mailbox_client.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
@@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent)
struct device *dev = &pdev->dev;
struct irq_domain *parent_domain;
struct generic_pm_domain *genpd;
+ struct device_node *msgram_np;
struct qcom_mpm_priv *priv;
unsigned int pin_cnt;
+ struct resource res;
int i, irq;
int ret;
@@ -374,9 +377,26 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent)
raw_spin_lock_init(&priv->lock);
- priv->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ /* If we have a handle to an RPM message ram partition, use it. */
+ msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0);
+ if (msgram_np) {
+ ret = of_address_to_resource(msgram_np, 0, &res);
+ if (ret) {
+ of_node_put(msgram_np);
+ return ret;
+ }
+
+ /* Don't use devm_ioremap_resource, as we're accessing a shared region. */
+ priv->base = devm_ioremap(dev, res.start, resource_size(&res));
+ of_node_put(msgram_np);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+ } else {
+ /* Otherwise, fall back to simple MMIO. */
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+ }
for (i = 0; i < priv->reg_stride; i++) {
qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0);