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authorRanjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>2022-02-07 09:52:08 +0800
committerJassi Brar <jaswinder.singh@linaro.org>2022-03-12 19:26:55 -0600
commit81a9d3b9301c9bb835d8ef595b2456084573db1b (patch)
tree7270c6b85af4b5e0ca5c2c6894fa8a7fb3c97bad /drivers/mailbox
parent8219efd08a0aa1d7944bdb66d84ba57549258968 (diff)
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mailbox: imx: enlarge timeout while reading/writing messages to SCFW
Mailbox driver needs to wait and read all the words in response to a SCFW API call, else the protocol gets messed up and results in kernel hang. When the responses are longer than 3 words its possible that SCFW will take some time to fill up the rest of the words in the MU, a timeout of 100us is arbritrary and too short. While waiting for Linux to consume the first 3 words of the response SCFW can be busy doing other stuff and hence Linux needs to wait for the rest of the words. Similar restriction applies when writing messages that are longer than 3 words. This patch increases the timeout to 5secs while waiting for response or writing long messages to SCFW. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Diffstat (limited to 'drivers/mailbox')
-rw-r--r--drivers/mailbox/imx-mailbox.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index a0c252415c86..a29f8006ad0d 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -218,7 +218,7 @@ static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
xsr,
xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
- 0, 100);
+ 0, 5 * USEC_PER_SEC);
if (ret) {
dev_err(priv->dev, "Send data index: %d timeout\n", i);
return ret;
@@ -263,7 +263,8 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
for (i = 1; i < size; i++) {
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
- xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100);
+ xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,
+ 5 * USEC_PER_SEC);
if (ret) {
dev_err(priv->dev, "timeout read idx %d\n", i);
return ret;