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| author | Dmitry Osipenko <digetx@gmail.com> | 2019-04-12 01:12:48 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-04-18 11:35:55 +0200 |
| commit | b906c056b6023c390f18347169071193fda57dde (patch) | |
| tree | 78c7872a2cabbb2c76478c66cd012d5ecfb759b0 /drivers/memory | |
| parent | 76b959a44c0b9c60cd41627cecb022c78042ad74 (diff) | |
| download | linux-b906c056b6023c390f18347169071193fda57dde.tar.gz linux-b906c056b6023c390f18347169071193fda57dde.tar.bz2 linux-b906c056b6023c390f18347169071193fda57dde.zip | |
memory: tegra: Fix integer overflow on tick value calculation
Multiplying the Memory Controller clock rate by the tick count results
in an integer overflow and in result the truncated tick value is being
programmed into hardware, such that the GR3D memory client performance is
reduced by two times.
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory')
| -rw-r--r-- | drivers/memory/tegra/mc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 1735e23dbc28..483ac3c1a762 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -285,7 +285,7 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) u32 value; /* compute the number of MC clock cycles per tick */ - tick = mc->tick * clk_get_rate(mc->clk); + tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); do_div(tick, NSEC_PER_SEC); value = readl(mc->regs + MC_EMEM_ARB_CFG); |