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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2020-05-29 13:13:03 +0200 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2020-06-26 08:35:05 +0200 |
| commit | adcf98b2d87429dfbc114666a8be6f2b36f5d898 (patch) | |
| tree | f6f5115ed88737f2d263128188daa6737d953092 /drivers/mtd/nand/raw | |
| parent | fe7f7b0846bdcc53a3d3e83fea67f988ab5145d8 (diff) | |
| download | linux-adcf98b2d87429dfbc114666a8be6f2b36f5d898.tar.gz linux-adcf98b2d87429dfbc114666a8be6f2b36f5d898.tar.bz2 linux-adcf98b2d87429dfbc114666a8be6f2b36f5d898.zip | |
mtd: rawnand: Rename nand_has_setup_data_iface()
This is really a NAND controller hook so call it
nand_controller_can_setup_data_iface(), which makes much more sense.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Link: https://lore.kernel.org/linux-mtd/20200529111322.7184-10-miquel.raynal@bootlin.com
Diffstat (limited to 'drivers/mtd/nand/raw')
| -rw-r--r-- | drivers/mtd/nand/raw/internals.h | 2 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/nand_base.c | 6 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/nand_legacy.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/drivers/mtd/nand/raw/internals.h b/drivers/mtd/nand/raw/internals.h index a518acfd9b3f..a5e2cec7e301 100644 --- a/drivers/mtd/nand/raw/internals.h +++ b/drivers/mtd/nand/raw/internals.h @@ -130,7 +130,7 @@ static inline int nand_exec_op(struct nand_chip *chip, return chip->controller->ops->exec_op(chip, op, false); } -static inline bool nand_has_setup_data_iface(struct nand_chip *chip) +static inline bool nand_controller_can_setup_data_iface(struct nand_chip *chip) { if (!chip->controller || !chip->controller->ops || !chip->controller->ops->setup_data_interface) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 6e06ccf61aeb..2a477ce81165 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -910,7 +910,7 @@ static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) { int ret; - if (!nand_has_setup_data_iface(chip)) + if (!nand_controller_can_setup_data_iface(chip)) return 0; /* @@ -955,7 +955,7 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { mode, }; int ret; - if (!nand_has_setup_data_iface(chip)) + if (!nand_controller_can_setup_data_iface(chip)) return 0; /* Change the mode on the chip side (if supported by the NAND chip) */ @@ -1025,7 +1025,7 @@ static int nand_init_data_interface(struct nand_chip *chip) { int modes, mode, ret; - if (!nand_has_setup_data_iface(chip)) + if (!nand_controller_can_setup_data_iface(chip)) return 0; /* diff --git a/drivers/mtd/nand/raw/nand_legacy.c b/drivers/mtd/nand/raw/nand_legacy.c index d64791c06a97..848403dcae03 100644 --- a/drivers/mtd/nand/raw/nand_legacy.c +++ b/drivers/mtd/nand/raw/nand_legacy.c @@ -365,7 +365,7 @@ static void nand_ccs_delay(struct nand_chip *chip) * Wait tCCS_min if it is correctly defined, otherwise wait 500ns * (which should be safe for all NANDs). */ - if (nand_has_setup_data_iface(chip)) + if (nand_controller_can_setup_data_iface(chip)) ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000); else ndelay(500); |