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author | Mintz, Yuval <Yuval.Mintz@cavium.com> | 2017-06-20 16:00:02 +0300 |
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committer | David S. Miller <davem@davemloft.net> | 2017-06-20 12:34:07 -0400 |
commit | 9331dad1bb7f3438c27e4f57136b6ad683d11fe0 (patch) | |
tree | 214dc8108e0dcecc99cd676e3f584f7eb87ed2b8 /drivers/net/ethernet/qlogic/qed/qed_roce.c | |
parent | 26462ad9c7ea18643f1a37adeab8b7eff6c5f5f4 (diff) | |
download | linux-9331dad1bb7f3438c27e4f57136b6ad683d11fe0.tar.gz linux-9331dad1bb7f3438c27e4f57136b6ad683d11fe0.tar.bz2 linux-9331dad1bb7f3438c27e4f57136b6ad683d11fe0.zip |
qed: Disable RoCE dpm when DCBx change occurs
If DCBx update occurs while QPs are open, stop sending edpms until all
QPs are closed.
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/qlogic/qed/qed_roce.c')
-rw-r--r-- | drivers/net/ethernet/qlogic/qed/qed_roce.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/net/ethernet/qlogic/qed/qed_roce.c b/drivers/net/ethernet/qlogic/qed/qed_roce.c index 4bc2f6c47f69..8419dcc111d8 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_roce.c +++ b/drivers/net/ethernet/qlogic/qed/qed_roce.c @@ -162,6 +162,11 @@ static int qed_bmap_test_id(struct qed_hwfn *p_hwfn, return test_bit(id_num, bmap->bitmap); } +static bool qed_bmap_is_empty(struct qed_bmap *bmap) +{ + return bmap->max_count == find_first_bit(bmap->bitmap, bmap->max_count); +} + static u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id) { /* First sb id for RoCE is after all the l2 sb */ @@ -2638,6 +2643,23 @@ static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev) return QED_LEADING_HWFN(cdev); } +static bool qed_rdma_allocated_qps(struct qed_hwfn *p_hwfn) +{ + bool result; + + /* if rdma info has not been allocated, naturally there are no qps */ + if (!p_hwfn->p_rdma_info) + return false; + + spin_lock_bh(&p_hwfn->p_rdma_info->lock); + if (!p_hwfn->p_rdma_info->cid_map.bitmap) + result = false; + else + result = !qed_bmap_is_empty(&p_hwfn->p_rdma_info->cid_map); + spin_unlock_bh(&p_hwfn->p_rdma_info->lock); + return result; +} + static void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { u32 val; @@ -2650,6 +2672,20 @@ static void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm); } +void qed_roce_dpm_dcbx(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) +{ + u8 val; + + /* if any QPs are already active, we want to disable DPM, since their + * context information contains information from before the latest DCBx + * update. Otherwise enable it. + */ + val = qed_rdma_allocated_qps(p_hwfn) ? true : false; + p_hwfn->dcbx_no_edpm = (u8)val; + + qed_rdma_dpm_conf(p_hwfn, p_ptt); +} + void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { p_hwfn->db_bar_no_edpm = true; |