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| author | Alexandru Ardelean <alexandru.ardelean@analog.com> | 2019-08-16 16:10:05 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-08-16 11:56:25 -0700 |
| commit | f1012fb476082c8983251a1991183964502ea855 (patch) | |
| tree | a24364736ee07e507ab216fb5142309c7cfcae52 /drivers/net/phy | |
| parent | c83e6163d852148e352181efab7e82f4cf0aa483 (diff) | |
| download | linux-f1012fb476082c8983251a1991183964502ea855.tar.gz linux-f1012fb476082c8983251a1991183964502ea855.tar.bz2 linux-f1012fb476082c8983251a1991183964502ea855.zip | |
net: phy: adin: make RMII fifo depth configurable
The FIFO depth can be configured for the RMII mode. This change adds
support for doing this via device-tree (or ACPI).
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy')
| -rw-r--r-- | drivers/net/phy/adin.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index c882fcd9ada5..4ca685780622 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -52,8 +52,19 @@ #define ADIN1300_RGMII_2_40_NS 0x0007 #define ADIN1300_GE_RMII_CFG_REG 0xff24 +#define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4) +#define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \ + FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x) #define ADIN1300_GE_RMII_EN BIT(0) +/* RMII fifo depth values */ +#define ADIN1300_RMII_4_BITS 0x0000 +#define ADIN1300_RMII_8_BITS 0x0001 +#define ADIN1300_RMII_12_BITS 0x0002 +#define ADIN1300_RMII_16_BITS 0x0003 +#define ADIN1300_RMII_20_BITS 0x0004 +#define ADIN1300_RMII_24_BITS 0x0005 + /** * struct adin_cfg_reg_map - map a config value to aregister value * @cfg value in device configuration @@ -73,6 +84,16 @@ static const struct adin_cfg_reg_map adin_rgmii_delays[] = { { }, }; +static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = { + { 4, ADIN1300_RMII_4_BITS }, + { 8, ADIN1300_RMII_8_BITS }, + { 12, ADIN1300_RMII_12_BITS }, + { 16, ADIN1300_RMII_16_BITS }, + { 20, ADIN1300_RMII_20_BITS }, + { 24, ADIN1300_RMII_24_BITS }, + { }, +}; + static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg) { size_t i; @@ -156,6 +177,7 @@ static int adin_config_rgmii_mode(struct phy_device *phydev) static int adin_config_rmii_mode(struct phy_device *phydev) { + u32 val; int reg; if (phydev->interface != PHY_INTERFACE_MODE_RMII) @@ -169,6 +191,13 @@ static int adin_config_rmii_mode(struct phy_device *phydev) reg |= ADIN1300_GE_RMII_EN; + val = adin_get_reg_value(phydev, "adi,fifo-depth-bits", + adin_rmii_fifo_depths, + ADIN1300_RMII_8_BITS); + + reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK; + reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val); + return phy_write_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG, reg); } |