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| author | Shawn Lin <shawn.lin@rock-chips.com> | 2017-05-02 15:31:23 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-07-02 18:45:54 -0500 |
| commit | e47ced77837153bdc962bf6f988c5da51a438568 (patch) | |
| tree | c7e37c9b1d78e54bfc2dd4c21449e068490bdb4a /drivers/pci | |
| parent | 769b461fc0c0451bacf75826d5830fc07c5a57e4 (diff) | |
| download | linux-e47ced77837153bdc962bf6f988c5da51a438568.tar.gz linux-e47ced77837153bdc962bf6f988c5da51a438568.tar.bz2 linux-e47ced77837153bdc962bf6f988c5da51a438568.zip | |
PCI: rockchip: Control vpcie0v9 for system PM
vpcie0v9 is used for PHY, so we could disable it as we don't need PHY to
work then in S3 if folks assign it DT. But we should note that there is a
side effect that we could not support beacon wakeup if we disable vpcie0v9
for aggressive power-saving.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pcie-rockchip.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 29332ba06bc1..5e4f758044d4 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -1251,6 +1251,9 @@ static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev) clk_disable_unprepare(rockchip->aclk_perf_pcie); clk_disable_unprepare(rockchip->aclk_pcie); + if (!IS_ERR(rockchip->vpcie0v9)) + regulator_disable(rockchip->vpcie0v9); + return ret; } @@ -1259,6 +1262,14 @@ static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev) struct rockchip_pcie *rockchip = dev_get_drvdata(dev); int err; + if (!IS_ERR(rockchip->vpcie0v9)) { + err = regulator_enable(rockchip->vpcie0v9); + if (err) { + dev_err(dev, "fail to enable vpcie0v9 regulator\n"); + return err; + } + } + clk_prepare_enable(rockchip->clk_pcie_pm); clk_prepare_enable(rockchip->hclk_pcie); clk_prepare_enable(rockchip->aclk_perf_pcie); |