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| author | Thierry Reding <treding@nvidia.com> | 2019-06-21 17:19:32 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-06-25 15:35:58 +0200 |
| commit | cf75b8f2cd8f1f9beb64c2fa2eb93a7c265b59c1 (patch) | |
| tree | 51b11e4427e8b18a0b826a9f339286710f923e2f /drivers/pinctrl/qcom | |
| parent | 55bd054ce434bb4aad80f6b787d69d29342bd4a8 (diff) | |
| download | linux-cf75b8f2cd8f1f9beb64c2fa2eb93a7c265b59c1.tar.gz linux-cf75b8f2cd8f1f9beb64c2fa2eb93a7c265b59c1.tar.bz2 linux-cf75b8f2cd8f1f9beb64c2fa2eb93a7c265b59c1.zip | |
pinctrl: tegra: Add bitmask support for parked bits
Some pin groups have park bits for multiple pins in one register.
Support this by turning the parked bit field into a parked bitmask
field. If no parked bits are supported, the bitmask can be 0.
Update the pingroup table on Tegra210, which is the only generation
where this is supported, with the parked bitmask.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/qcom')
0 files changed, 0 insertions, 0 deletions