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| author | Jon Hunter <jonathanh@nvidia.com> | 2022-10-28 13:33:55 +0100 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@gmail.com> | 2022-11-09 18:30:52 +0100 |
| commit | f271946117dde2ca8741b8138b347b2d68e6ad56 (patch) | |
| tree | d0c3269fc8dfc57ff93f8531e6767720721ada8e /drivers/pwm | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
| download | linux-f271946117dde2ca8741b8138b347b2d68e6ad56.tar.gz linux-f271946117dde2ca8741b8138b347b2d68e6ad56.tar.bz2 linux-f271946117dde2ca8741b8138b347b2d68e6ad56.zip | |
pwm: tegra: Improve required rate calculation
For the case where dev_pm_opp_set_rate() is called to set the PWM clock
rate, the requested rate is calculated as ...
required_clk_rate = (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
The above calculation may lead to rounding errors because the
NSEC_PER_SEC is divided by 'period_ns' before applying the
PWM_DUTY_WIDTH multiplication factor. For example, if the period is
45334ns, the above calculation yields a rate of 5646848Hz instead of
5646976Hz. Fix this by applying the multiplication factor before
dividing and using the DIV_ROUND_UP macro which yields the expected
result of 5646976Hz.
Fixes: 1d7796bdb63a ("pwm: tegra: Support dynamic clock frequency configuration")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
| -rw-r--r-- | drivers/pwm/pwm-tegra.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index dad9978c9186..b05ea2e8accc 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -145,8 +145,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * source clock rate as required_clk_rate, PWM controller will * be able to configure the requested period. */ - required_clk_rate = - (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; + required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH, + period_ns); err = dev_pm_opp_set_rate(pc->dev, required_clk_rate); if (err < 0) |