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| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2019-08-16 12:41:54 -0700 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-11-11 14:53:03 +0100 |
| commit | 68a14a5634dacb37d18618d62f0410f1ec69ab28 (patch) | |
| tree | 2b61253f1544ba705f9830832540e212045b1e6e /drivers/soc/qcom | |
| parent | 2b8cfd6b52cbf951d9b90862d95b8473d34d02ee (diff) | |
| download | linux-68a14a5634dacb37d18618d62f0410f1ec69ab28.tar.gz linux-68a14a5634dacb37d18618d62f0410f1ec69ab28.tar.bz2 linux-68a14a5634dacb37d18618d62f0410f1ec69ab28.zip | |
clk: tegra: clk-super: Fix to enable PLLP branches to CPU
This patch has a fix to enable PLLP branches to CPU before changing
the CPU cluster clock source to PLLP for Gen5 Super clock and
disables PLLP branches to CPU when not in use.
During system suspend entry and exit, CPU source will be switched
to PLLP and this needs PLLP branches to be enabled to CPU prior to
the switch.
On system resume, warmboot code enables PLLP branches to CPU and
powers up the CPU with PLLP clock source.
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/soc/qcom')
0 files changed, 0 insertions, 0 deletions